1. Field of the Invention
This invention relates to a display device, and more particularly to an improved plasma display panel (PDP) for displaying a picture with the aid of a discharge caused by an alternating current voltage signal. Also, this invention is directed to an improved driving apparatus for the PDP.
2. Description of the Prior Art
Generally, display panels include a cathode ray tube (CRT), a liquid crystal display panel, a plasma display panel (PDP) and so on. The CRT has disadvantages in that its operational voltage is relatively high and that it is difficult to obtain a large-scale screen and a flat screen. The liquid crystal panel has inferior optical characteristics. Otherwise, in comparison to them, the PDP has advantages in that it is not only easy to obtain a large-scale screen and a flat screen, but also it has superior optical characteristics. Recently, the PDP has prevailed in the market owing to such advantages. Further, a plasma display apparatus employing the PDP controls a discharging interval for each picture element or pixel on the PDP, thereby to display moving pictures or still pictures. This plasma display apparatus, however, has a complex circuit configuration and experiences a severe electromagnetic interference, depending upon an electrode structure in the PDP.
An example of a conventional alternating current plasma display apparatus having such drawbacks is shown in FIG. 1. Referring to FIG. 1, the alternating current plasma display apparatus includes a PDP 10 having m.times.n pixels arranged in a matrix pattern, and a microcomputer 20 for converting picture data containing red (R), green (G), and blue (B)pixel data into panel picture data and for generating control signals. As shown in FIG. 2, each of m.times.n pixels included in the PDP 10 is composed of three color pixel cells, i.e., R, G, and B pixel cells. Thus, the PDP 10 includes m.times.3n color pixel cells.
Referring now to FIG. 2, the m.times.3n color pixel cells are divided by a compartment wall 13 in a shape of matrix disposed between an upper substrate 11 and a lower substrate 12. The compartment wall 13 provides a discharging space for each m.times.n color pixel cells. In the upper substrate 11, as shown in FIG. 3, m Y sustain electrodes YE1, YE2, . . . , YEm arranged in parallel with respect to the vertical axis and m Z sustain electrodes ZE1, ZE2, . . . , ZEm arranged in an alternate pattern with respect to the Y sustain electrodes YE1, YE2, . . . , YEm are defined in such a manner to be unoverlapped with the compartment wall 13. Thus, one Y sustain electrode YE and one Z sustain electrode ZE are positioned at the upper portion of color pixel cells in one raw, i.e., one raw of discharging spaces. On the other hand, in the lower substrate 13, as shown in FIG. 3, n R, G, and B address electrodes RE1, GE1, BE1, RE2, GE2, . . . , BEn-1, REn, GEn, BEn are defined in a mutually alternate pattern in such a manner to be unoverlapped with the compartment wall 13. As a result, one R, G or B address electrode RE, GE or BE is positioned at the lower portion of color pixel cells in one column. Each R, G and B address electrodes RE1, GE1, BE1, RE2, GE2, . . . , BEn-1, REn, GEn, BEn causes a discharge between the Y sustain electrodes YE1, YE2, . . . , YEm and the Z sustain electrodes ZE1, ZE2, . . . , ZEm. Also, each Y sustain electrode YE1, YE2, . . . , YEm keeps the discharge caused between it and the Z sustain electrodes ZE1, ZE2, . . . , ZEm corresponding thereto. A dielectric material layer 15 and a MgO protective film 16 is sequentially disposed on the upper substrate 11 in which Y and Z sustain electrodes YE1, YE2, . . . , YEm and ZE1, ZE2, . . . , ZEm are formed. The dielectric material layer 15 is responsible for limiting a discharge current in each color pixel cell. The protective film 16 is responsible for protecting the dielectric material layer 15 and the Y and Z sustain electrodes YE1, YE2, . . . , YEm and ZE1, ZE2, . . . , ZEm from a sputtering accompanied during discharging in each color pixel cell. A R fluorescent body layer 14A is formed on the surface of each R address electrode RE1, RE2, . . . , REm; a G fluorescent body layer 14B is formed at the upper portion of each G address electrode GE1, GE2, . . . , GEm; and a B fluorescent body layer 14C is formed on the surface of each G address electrode GE1, GE2, . . . , GEm. The R, G and B fluorescent body layers 14A, 14B and 14C are usually formed to reach the vicinity of the upper end of the compartment wall 13. A discharge gas 17 is injected into each of color pixel cells divided by the compartment wall 13, i.e., discharge spaces. This discharge gas emits a light 18 such as ultraviolet lays when a discharge is generated among the Y sustain electrode YE, the Z sustain electrode ZE, and/or the address electrode RE, GE or BE. The R, G and B fluorescent bodies 14A, 14B and 14C brightens by means of the light from the discharge gas 17, thereby displaying a picture on the PDP 10.
Returning to FIG. 1, panel picture data generated at the microcomputer 20 contains x subfield picture data SF1 to SFx for on frame picture data corresponding to a single picture. In other words, one frame field picture data consist of x subfield picture data SF1 to SFx. Each color pixel cell on the PDP 10 is discharged or undischarged by the subfield picture data SF. The x subfield picture data SF1 to SFx are made by separating x bits of R, G and B pixel data for each bit thereof. Thus, the first subfield picture data SF1 contain the least significant bits of R, G, and B pixel data; the second subfield picture data SF2 contain the next order significant bits of R, G, and B pixel data; and the x numbered subfield picture data SFx contain the most significant bits of R, G, and B pixel data.
Further, the plasma display apparatus includes a memory 30 for temporarily storing panel picture data from the microcomputer 20, and a Y sustain driver 40 and a Z sustain driver 50 for receiving control signals from the microcomputer 20. The memory 30 stores panel picture data while dividing the same for frame, for subfield (i.e., for bit) and for color thereof. The Y sustain driver 40 is responsive to the control signals from the microcomputer 20 to sequentially drive m Y sustain electrode lines YE1, YE2, . . . , YEm every subfield. Specifically, the Y sustain driver 40 applies an erase pulse to all the m Y sustain electrode lines YE1, YE2, . . . , YEm to thereby eliminate electric charges charged into a side wall 13 in the previous subfield, hereinafter referred to as "wall charges", and then applies a write pulse to all the m Y sustain electrode lines YE1, YE2, . . . , YEm to thereby uniformly charge wall charges into the side wall 13 of the PDP 10. Subsequently, the Y sustain driver 40 sequentially applies to the m Y sustain electrode lines YE1, YE2, . . . , YEm to thereby sequentially drive the color pixel cells on the PDP 10 for one line. To this end, the Y sustain driver 40 includes l Y driving integrated circuit (IC) chips. The l Y driving IC chips drive the m Y sustain electrode lines YE1, YE2, . . . , YEm while dividing them into three units. Likewise, the Z sustain driver 50 is responsive to the control signals from the microcomputer 20 to sequentially drive m Z sustain electrode lines ZE1, ZE2, . . . , ZEm every subfield. Specifically, the Z sustain driver 50 applies an erase pulse to all the m Z sustain electrode lines ZE1, ZE2, . . . , ZEm to thereby eliminate electric charges charged into the side wall in the previous subfield, that is, wall charges, and then applies a write pulse to all the m Y sustain electrode lines YE1, YE2, . . . , YEm to thereby uniformly charge wall charges into the side wall 13 of the PDP 10. Subsequently, the Z sustain driver 50 sequentially applies a sustain pulse to the m Z sustain electrode lines ZE1, ZE2, . . . , ZEm to thereby sequentially drive the color pixel cells on the PDP 10 for one line. To this end, the Z sustain driver 40 includes l Z driving IC chips. The l Z driving IC chips drive the m Z sustain electrode lines ZE1, ZE2, . . . , ZEm while dividing them into three units. Pulse signals generated at the Y sustain driver 40 has a contrary waveform to pulse signals at the Z sustain driver 50. Also, the sustain pulses generated at the Y sustain driver 40 and the sustain pulses generated at the Z sustain driver 50 have wavelengths incrementing by 2.sup.n in proportion to a progress of the subfields. In other words, the sustain pulses have wavelengths of 2.sup.0, 2.sup.1, 2.sup.2, . . . , 2.sup.x-2, 2.sup.x-1 in the 1st to xth subfields, respectively. A discharge generating between the Y sustain electrode line YE and the Z sustain electrode line ZE by the sustain pluses maintains for each interval corresponding to 2.sup.0, 2.sup.1, 2.sup.2, . . . , 2.sup.x-2, 2.sup.x-1 in accordance with a progress of the subfields.
Furthermore, the plasma display apparatus includes first and second address driver 61 and 62 for divisionally receiving panel picture data from the memory 30. The first address driver 61 drives m times odd-numbered address electrode lines RE1, BE1, GE2, RE3, BE3, GE3, . . . , REn-1, BEn-1, Gn in the n R, G, and B address electrode lines RE1, GE1, BE1, RE2, GE2, . . . , BEn-1, REn, GEn, BEn. To this end, the first address driver 61 applies an erase pulse to all the odd-numbered address electrode lines RE1, BE1, GE2, RE3, BE3, GE3, . . . , REn-1, BEn-1, Gn every subfield to thereby form wall charges on the surface of the R, G, or B fluorescent material layers 14A, 14B and 14C included in each odd-numbered color pixel cell. Then, the first address driver 61 receives m times odd-numbered pixel data R1, B1, G2, R3, B3, . . . , Rn-1, Bn-1, Gn corresponding to the odd-numbered address electrode lines RE1, BE1, GE2, RE3, BE3, GE3, . . . , REn-1, BEn-1, Gn from the memory 30. This results from the Y sustain driver 40 and the Z sustain driver 50 driving m Y sustain electrode lines YE1, YE2, . . . , YEm and m Z sustain electrode lines ZE1, ZE2, . . . , ZEm sequentially for one line. In addition, each time the odd-numbered pixel data R1, B1, G2, R3, B3, . . . , Rn-1, Bn-1, Gn is inputted, the first address driver 61 selectively applies an address pulse to each odd-numbered address electrode lines RE1, BE1, GE2, RE3, BE3, GE3, . . . , REn-1, BEn-1, Gn in accordance with a logical value of each pixel data, thereby selectively causing a discharge in each discharge space of the odd-numbered color pixel cells. The address pulse is generated in such a manner to be synchronized with a scan pulse stream only when a logical value of the pixel data is "1" and applied to the address electrode line. The discharge selectively generating at each discharge space of the odd-numbered color pixel cells in the above manner is maintained during an interval in which the sustain pulse is applied to the Y sustain electrode line YE and the Z sustain electrode line ZE. During the interval maintaining the discharge, discharge gases 17 contained in each discharge space of the odd-numbered color pixel cells emit ultraviolet lays 18 to brighten the R, G and B fluorescent layers 14A, 14B and 14C. The ultraviolet rays 18 is generated when electrons included in gas particles are excited and then transited. The electrons are excited by absorbing an energy generated when gas particles collide with respect to each other. Likewise, the second address driver 62 drives m times even-numbered address electrode lines GE1, RE2, BE2, GE3, . . . , GEn-1, REn-1, Bn in the n R, G, and B address electrode lines RE1, GE1, BE1, RE2, GE2, . . . , BEn-1, REn, GEn, BEn. To this end, the second address driver 62 applies an erase pulse to all the even-numbered address electrode lines GE1, RE2, BE2, GE3, . . . , GEn-1, REn-1, Bn every subfield, to thereby form wall charges on the surface of the R, G, or B fluorescent material layers 14A, 14B and 14C included in each even-numbered color pixel cell. Then, the second address driver 62 receives m times even-numbered pixel data G1, R2, B2, G3, . . . , Gn-1, Rn, Bn corresponding to the even-numbered address electrode lines GE1, RE2, BE2, GE3, . . . , GEn-1, REn-1, Bn the memory 30. The first address driver 61 and the second address driver 62 generate an erase pulse in such a manner that the erase pulse is positioned between a write pulse generated at the sustain drivers 40 and 50 and the sustain pulse stream. In addition, each time the even-numbered pixel data G1, R2, B2, G3, . . . , Gn-1, Rn, Bn are inputted, the second address driver 62 selectively applies an address pulse to each even-numbered address electrode lines GE1, RE2, BE2, GE3, GEn-1, REn-1, Bn in accordance with a logical value of each pixel data, thereby selectively causing a discharge in each discharge space of the even-numbered color pixel cells. The discharge selectively generating at each discharge space of the even-numbered color pixel cells in the above manner is maintained during an interval in which a scan pulse stream is applied to the Y sustain electrode line YE and the Z sustain electrode line ZE. During the interval maintaining the discharge, discharge gases 17 contained in each discharge space of the even-numbered color pixel cells emit ultraviolet lays 18 to brighten the R, G and B fluorescent layers 14A, 14B and 14C. As a result, each even-numbered color pixel cell included in the PDP 10 selectively emits R, G or B lights through the lower glass substrate 12.
As described above, the color pixel cells included in the PDP 10 is selectively driven every subfield by means of the address drivers 61 and 62 and the sustain drivers 40 and 50, thereby generating R, G or B lights at each color pixel cell only during any one of 2.sup.x intervals in an interval when a single picture is displayed, that is, in one frame interval. In other words, a total amount of the R, G or B lights generated during one frame interval at each color pixel cell included in the PDP 10 has any one of 2.sup.x scale levels. Thus, 2.sup.x gray levels of R, G or B are displayed on each color pixel cell and, therefore, 2.sup.x gray levels of color picture is displayed on the PDP 10.
In the conventional plasma display apparatus as mentioned above, since a sustain pulse stream is sequentially applied to the sustain electrode lines at the PDP 10 in such a manner to be applied to one sustain electrode line, circuit configurations of the Y and Z sustain drivers becomes complicated and the frequency of the sustain pulse becomes high. Such a rise in the frequency of the sustain pulse in the conventional display apparatus results in a lot of power consumption as well as a shortened life of the PDP. Further, in the conventional plasma display apparatus, since the address electrode lines at the PDP is divided into the odd-numbered address electrode lines and the even-numbered address electrode lines and driven, all R, G and B pixel data must be supplied to each of the first address driver driving the odd-numbered address electrode lines and the second address driver driving the even-numbered address electrode lines. Due to this, a cross talk between data occurs at the data transfer path between the memory and the address driver and thus a noise caused by the cross talk between data is produced. As a result the conventional plasma display apparatus has an inferior picture quality.
As an alternative for simplifying the circuit configuration, a plasma display apparatus connecting all Z sustain electrode lines in parallel is disclosed in Japanese Laid-open Patent No. Puyng 5-266800. The plasma display apparatus in the Japanese Patent provides an advantage in that the Z sustain driver can be omitted. The display apparatus, however, allows a discharge current in each color pixel to be flow toward the same direction. Due to this, the display apparatus appears causes more severe electromagnetic interference.